1. Field of the Invention
The present invention relates to semiconductor wafer deposition and planarization and, more particularly, to apparatuses and techniques for more effectively depositing thin films using localized deposition and for enabling localized planarization.
2. Description of the Related Art
Electroplating is a well-established deposition technology. In the semiconductor fabrication arts, electroplating is typically performed in a single-wafer processor, with the wafer immersed in an electrolyte. During electroplating, the wafer is typically held in a wafer holder, at a negative, or ground potential, with respect to a positively charged plate (also immersed in the electrolyte) which acts as an anode. To form a copper layer, for example, the electrolyte is typically between about 0.3M and about 0.85M CuSO4, pH between about 0 and about 2 (adjusted by H2SO4), with trace levels (in ppm concentrations) of proprietary organic and/or inorganic additives to enhance the deposited material quality.
During the plating process the wafer is typically rotated to facilitate uniform plating. After a sufficient film thickness has been achieved during the plating process, the wafer is moved from the plating chamber to another chamber where it is rinsed in de-ionized (DI) water to remove residual electrolyte from the wafer surface. Next the wafer is subjected to additional wet processing, to remove unwanted copper from the backside and bevel edge, and then another DI water rinse removes wet processing chemical residues. Then the wafer is dried and annealed before it is ready for chemical mechanical planarization (CMP) operations. Unlike processing wafers in vacuum environments, “wet” operations during wafer processing are followed by an additional DI water rinse and drying step. Due to electrolyte dilution concerns and increased hardware design complexity, DI water rinsing is typically not done within the plating chamber. Today, approximately fifty percent of the wet processing stations on wafer plating tools are dedicated to plating, having a significant negative impact on wafer throughput and increasing processing cost. In addition, in order to enable direct copper plating on a barrier layer, the amount of time between surface activation and plating must be minimized. The effectiveness of the surface activation operation is limited by additional time taken to rinse a wafer after surface activation and to transport the wafer to the plating module. Eliminating or reducing the amount of separate DI water rinses between wet processing steps provides a more efficient methodology.
During a plating process, the wafer acts as a cathode requiring that a power supply be electrically connected to the wafer. Typically, numerous discrete contacts on a wafer holder or support connect the wafer holder electrically to the edge of the wafer. Electrical current provided through these contacts is utilized to electroplate the wafer. In the traditional approach, plating current is evenly distributed around the perimeter of the wafer with the goal of providing uniform deposition. Uniform deposition typically requires uniform and consistent contact resistance with the wafer through a resistive seed layer. Therefore, in an effort to provide uniform deposition, cleanliness and repeatability of the contacts to the substrate is preferred. In some cases, cleaning of the contacts requires additional processes that further limit the productivity of plating operations.
Bipolar effects are another challenge in copper electroplating, and are observed when contact resistance is very high. Bipolar effects occur when wet contacts are used in the plating process. This effect induces etching of the copper seed layer directly under the contacts, thereby severing the electrical contact between the wafer and the power supply during electroplating. Bipolar effects are avoided when dry contacts are used, however dry contact methods require complicated seal design and are prone to reliability problems. As feature dimensions on semiconductor wafers continue to shrink, copper seed layer thickness is also expected to decrease, from approximately 1000 angstroms today to less than about 400 angstroms. Thickness reduction of the seed layer is necessary to ensure a reasonable sized opening at the top of the features so as to enable void free gap fill during the copper electroplating process. Since the role of the seed layer is to distribute the plating current over the entire wafer during electroplating, a thinner more resistive seed layer introduces a significant challenge in chambers designed for uniform plating near contacts on the wafer periphery. Known as the terminal effect, this effect is more pronounced on larger wafers, such as today's 300 mm wafers.
What is needed therefore, is an electroplating system that provides uniform electroplating on barrier layers of semiconductor wafers without bipolar effects.